1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more specifically to a NAND type non-volatile semiconductor memory device having a memory cell array in which NAND type memory cells are arranged in a matrix pattern.
2. Description of the Prior Art
Recently, there is a great demand for non-volatile semiconductor memory devices, because data are not erased even if the voltage supply is turned off. In the case of flash memory as a simultaneous erasable non-volatile semiconductor memory device, it is possible to construct the memory cell by a single transistor, being different from two-transistor bite-type non-volatile semiconductor memory device in which data can be erased per bite. Among these, in the NAND type EEPROM (electrically erasable and programmable read only memory), since the number of bit line contacts per unit cell can be reduced markedly, it is possible to realize a high density memory cell array. As a result, since the memory cell size can be reduced effectively, the NAND type EEPROM is expected as a use of a substitute for a large capacity magnetic disk.
In the NAND type EEPROM, the memory cell array is constructed by arranging NAND type memory cells in a matrix pattern. Here, the memory cells are composed of series cells formed by connecting memory cell transistors (MOS transistors each having a floating gate) in series, source side select transistors each having a gate connected to a source side select line provided between one end of the series-connected memory cells and a common source line, and drain side select transistors provided between the other end of the series connected memory cells and the bit lines.
In operation, when charges are accumulated at the floating gates of the respective memory cell transistors, since the threshold values of the MOS transistors change, information data can be stored on the basis of change in the threshold value. Further, information data can be written and erased in and from the memory cells by flowing a tunnel current through an insulating film.
In the NAND type EEPROM as described above, however, since a relatively high voltage (e.g., 20 V) is used to write and erase data, it is necessary to suppress leak current from flowing between the adjacent memory cells as much as possible, so that the impurity concentration is determined to be relatively high in a channel stopper layer under a field insulating film used as the element separating region. Consequently, the threshold values of the series-connected transistors increase due to the narrow channel effect (i.e., due to diffusion in the transversal direction in the channel stopper layer), with the result that there arise various problems in that the serial resistance of the NAND type memory cells increases; an erroneous data read occurs due to a decrease in the current flowing the NAND type memory cells in read mode; and data read speed is reduced due to the decrease in the read current.
As described above, in the conventional NAND type EEPROM, since the concentration of the channel stopper layer used as the element separating region must be determined to be high to suppress the leak current flowing between adjacent memory cells, the data read current is inevitably reduced, thus causing problems in that data are read erroneously and the data read speed is reduced.